The present invention relates to displays, and more particularly to processes for forming spacers in a field emission display (FED).
Referring to FIG. 1, in a typical FED (a type of flat panel display), a cathode 21 has a substrate 11 of single crystal silicon or glass. Conductive layers 12, such as doped polysilicon or aluminum, are formed on substrate 11. Conical emitters 13 are constructed on conductive layers 12. Surrounding emitters 13 are a dielectric layer 14 and a conductive extraction grid 15 formed over dielectric layer 14. When a voltage differential from a power source 20 is applied between conductive layers 12 and grid 15, electrons 17 bombard pixels 22 of a phosphor coated faceplate (anode) 24. Faceplate 24 has a transparent dielectric layer 16, preferably glass, a transparent conductive layer 26, preferably indium tin oxide (ITO), a black matrix grille (not shown) formed over conductive layer 26 and defining regions, and phosphor coating over regions defined by the grille.
Cathode 21 may be formed on a backplate or it can be spaced from a separate backplate. In either event, cathode 21 and faceplate 24 are spaced very close together in a vacuum sealed package. In operation, there is a potential difference on the order of 1000 volts between conductive layers 12 and 26. Electrical breakdown must be prevented in the FED, while the spacing between the plates must be maintained at a desired thinness for high image resolution.
A small area display, such as one inch (2.5 cm) diagonal, may not require additional supports or spacers between faceplate 24 and cathode 21 because glass substrate 16 in faceplate 24 can support the atmospheric load. For a larger display area, such as a display with a thirty inch (75 cm) diagonal, several tons of atmospheric force will be exerted on the faceplate, thus making spacers important if the faceplate is to be thin and lightweight.